Conventional memory array, such a flash memory array, typically includes one or more high-density core regions and a low-density periphery region on a single substrate. Memory transistors in the core have a substantially similar stacked gate structure. The stacked gate structure includes a floating gate comprising a first layer of polysilicon (poly 1) underneath a control gate. The control gate comprises a second layer of polysilicon (poly 2).
Processing steps for fabricating a memory array, such as a flash memory array, include, among other steps, forming a gate oxide layer and isolation regions in core and peripheral regions of a substrate. Poly 1 is deposited over the gate oxide layer and the isolation regions and a chemical mechanical polish (“CMP”) process is typically used to planarize the poly 1 in the core region while a hard mask protects the poly 1 in the peripheral region of the substrate. As a result of the CMP process, poly 1 segments are formed between isolation regions such that the top surfaces of the poly 1 segments and the top surfaces of the isolation regions form a planar surface.
In a conventional fabrication process, a CMP “over-polish” process is typically performed to reduce the thickness of the poly 1 segments to a desired final thickness. However, the CMP “over-polish” process causes undesirable core erosion without providing good stopping capability. As a result, an accurate final thickness of poly 1 segments is difficult to achieve by using the CMP “over-polish process. Furthermore, the CMP “over-polish” process causes undesirable non-uniformity in the poly 1 segments, which undesirably affects a subsequent gate etch process.
Thus, there is a need in the art for a method of fabricating a memory array, such as a flash memory array, that achieves a desired poly 1 final thickness while avoiding undesirable non-uniformity and core erosion caused by a CMP “over-polish” process.